1. Field of the Invention
The present invention relates to depletion-mode transistors and, more particularly, to a method of forming a depletion-mode transistor that eliminates the need to separately set the threshold voltage of the depletion-mode transistor.
2. Description of the Related Art
MOS transistors typically fall into one of two classifications; a depletion-mode transistor or an enhancement-mode transistor. A depletion-mode transistor is a transistor that conducts (more than a leakage current) when the gate, source, and bulk are at the same potential, such as ground for an NMOS transistor and a positive voltage for a PMOS transistor. Depletion-mode transistors are commonly turned off by placing a voltage on the gate that is less than the source voltage for the NMOS transistor, and greater than the source voltage for the PMOS transistor.
An enhancement-mode transistor, on the other hand, is a transistor that is non-conductive (except for leakage currents) when the gate, source, and bulk are at the same potential. Enhancement-mode transistors are commonly turned off by placing ground on the gate of the NMOS transistor and the positive voltage on the gate of the PMOS transistor.
Depletion-mode transistors, in an always-on state, are often used in semiconductor circuits to provide a resistive element. Typically, however, a separate mask and implant step are required during the fabrication of the semiconductor circuit to set the threshold voltage of the depletion-mode transistor.
FIGS. 1A-1I show a series of cross-sectional diagrams that illustrate a prior-art method of forming a semiconductor circuit that does not include depletion-mode transistors. As shown in FIG. 1A, the prior-art method utilizes a conventionally formed wafer 100 that includes a p+ substrate 110 and a p-type epitaxial layer 112 that is formed on substrate 110.
In addition, wafer 100 also includes a number of field oxide regions FOX that are formed in epitaxial layer 112, and a number of n-wells, including first and second n-wells 120 and 122, that are formed in epitaxial layer 112. N-well 120 is utilized to support a number of hight-voltage PMOS transistors, while n-well 122 is utilized to support a number of a low-voltage, high threshold voltage PMOS transistors.
Further, wafer 100 can include a number of p-type wells, including a first p-well 130, a second p-well 132, and a third p-well 134, that are formed in epitaxial layer 112. P-well 130 is utilized to support a number of EEPROM transistors. Second and third p-wells are utilized to support a number of high-voltage NMOS transistors, and a number of low-voltage, high threshold voltage NMOS transistors.
The prior-art method begins by forming a layer of screen oxide 140 on epitaxial layer 112, followed by the formation and patterning of a first implant mask 142 on oxide layer 140. Implant mask 142 is patterned to expose a number of regions on the surface of oxide layer 140 that correspond with a number of to-be-formed n+ buried regions in p-well 130.
The number of to-be-formed n+ buried regions, in turn, corresponds with the number of EEPROM transistors that are to be formed in p-well 130. Once implant mask 142 has been patterned, the exposed regions of oxide layer 140 are implanted with a dopant, such as phosphorous or arsenic, to form a number of n+ buried regions 144. Implant mask 142 is then removed.
Next, as shown in FIG. 1B, an NMOS threshold voltage mask 146 is formed and patterned on oxide layer 140. Threshold voltage mask 146 is patterned to expose a number of regions on the surface of oxide layer 140 that correspond with a number of to-be-formed memory channel regions 150 in p-well 130, a number of high-voltage NMOS channel regions 152 in p-well 132, and a number of low-voltage, high threshold voltage NMOS channel regions 154 in p-well 134.
Once threshold mask 146 has been patterned, the exposed regions of oxide layer 140 are implanted with a dopant, such as boron, to set the threshold voltages of the to-be-formed memory transistors in p-well 130 and high-voltage NMOS transistors in p-well 132, and partially set the threshold voltage of the low-voltage, high threshold voltage NMOS transistors in p-well 134. Threshold mask 146 is then removed.
Following this, a PMOS threshold voltage mask (not shown) is formed and patterned on oxide layer 140. The PMOS threshold voltage mask is patterned to expose a number of regions on the surface of oxide layer 140 that correspond with a number of to-be-formed high voltage PMOS channel regions 158 in n-well 120. Once the PMOS threshold mask has been patterned, the exposed regions of oxide layer 140 are implanted with a dopant, such as boron, to set the threshold voltages of the to-be-formed high-voltage PMOS transistors. The PMOS threshold mask is then removed. After this, screen oxide layer 140 is removed.
Next, as shown in FIG. 1C, a layer of gate oxide 160 is formed on epitaxial layer 112, followed by the formation and patterning of a tunneling mask 162 on oxide layer 160. Tunneling mask 162 is patterned to expose a number of regions on the surface of gate oxide layer 160 that overlie and correspond with the number of n+ buried regions 144. Once tunneling mask 162 has been patterned, the exposed regions of gate oxide layer 160 are etched until gate oxide layer 160 is removed from the surfaces of p-well 130 over n+ buried regions 144. Tunneling mask 162 is then stripped.
After this, as shown in FIG. 1D, a layer of tunnel oxide 166 is grown on the exposed surfaces of p-well 130. A first layer of polysilicon (poly-1) 170 is then formed on gate oxide layer 160 and tunnel oxide layer 166, and conventionally doped. Next, a layer of oxide 172 is formed on poly-1 layer 170, followed by the formation of an overlying layer of nitride 174, and an overlying layer of oxide 176. Oxide layer 172, nitride layer 174, and oxide layer 176 form an interpoly dielectric commonly known as ONO.
Once oxide layer 176 has been formed, a poly-1 mask 180 is formed and patterned on oxide layer 176. poly-1 mask 180 is patterned to protect a number of regions on the surface of oxide layer 176 that correspond with a number of gates of the to-be-formed high-voltage transistors and a number of floating gates of the to-be-formed EEPROM transistors.
Next, as shown in FIG. 1E, the exposed regions of oxide layer 176 and the underlying layers of nitride layer 174, oxide layer 172, and poly-1 layer 170 are etched until poly-1 layer 170 is removed from the underlying layer of gate oxide 160. The etch forms the floating gates 182 of the EEPROM transistors, the gates 184 of the high-voltage PMOS transistors, and the gates 186 of the high-voltage NMOS transistors.
Following this, wafer 100 is blanket implanted with a dopant, such as boron, to set the threshold voltage of the low-voltage, high threshold voltage PMOS transistors in n-well 122. The blanket implant also partially sets (finishes setting) the threshold voltage of the low-voltage, high threshold voltage NMOS transistors in p-well 134. Boron 11, for example, can be implanted at a dose of 3.57xc3x971012 at an implant energy of 22 KeV. poly-1 mask 180 is then stripped.
Next, as shown in FIG. 1F, an ONO protect mask 210 is formed and patterned on oxide layer 176. ONO protect mask 210 is patterned to protect oxide layer 176 overlying the floating gates 182 of the to-be-formed EEPROM transistors in p-well 130. Following this, oxide layer 176, nitride layer 174, and oxide layer 172 are removed from the regions that overlie gates 184 and 186 of the to-be-formed high-voltage PMOS and NMOS transistors in n-well 120 and p-well 132, respectively. Next, gate oxide layer 160 is etched. The etch removes gate oxide 160 from the surface of n-well 122 and p-well 134. Mask 210 is then removed.
As shown in FIG. 1G, following the removal of mask 210, a thin layer of oxide 212 is formed on the exposed surfaces of wafer 100, including n-wells 120-122, p-wells 130-134, gates 184 and 186 over wells 124 and 132, and oxide layer 176 over well 130.
Following this, a second layer of polysilicon (poly-2) 216 is formed on oxide layer 212, and conventionally doped (via tube doping). Next, a word line/gate mask 218 is formed and patterned on poly-2 layer 216. Word line/gate mask 218 is patterned to define a number of strips on the surface of poly-2 layer 216 that correspond with a number of to-be-formed word lines (word lines include the control gates) over p-well 130.
Word line/gate mask 218 is also patterned to define the gates of the to-be-formed low-voltage, high threshold voltage PMOS transistors in well 122, and low-voltage, high threshold voltage NMOS transistors in well 134. Once word line/gate mask 218 has been patterned, the exposed regions of poly-2 layer 216 are etched until the exposed regions of poly-2 layer 216 are removed from the surface of oxide layer 212. Mask 218 is then removed.
As shown in FIG. 1H, the etch of poly-2 layer 216 forms a number of word lines WL. The etch also forms the gate 222 of the to-be-formed low-voltage, high threshold voltage PMOS transistors in well 122. The etch additionally forms the gate 234 of the to-be-formed low-voltage, high threshold voltage NMOS transistors in well 134.
The etch further exposes regions of oxide layer 212 that correspond with a number of to-be-formed source regions, a number of to-be-formed drain regions, and a number of to-be-formed source lines. Next, a NMOS low-density source/drain (NLDD) mask 240 is formed and patterned on wafer 100 to protect the PMOS regions of oxide layer 212. The exposed regions of oxide layer 212 are implanted with a dopant, such as phosphorous or arsenic, to form a number of n-type low-density source and drain regions 242 in wells 130-134 (only a LDD source region is formed in well 130). NLDD mask 240 is then stripped.
After this, a PMOS low-density source/drain (PLDD) mask (not shown) is formed and patterned on wafer 100 to protect the NMOS regions of oxide layer 212. The exposed regions of oxide layer 212 are implanted with a dopant, such as boron, to form a number of p-type low-density source and drain regions 244 in wells 120-122. The PLDD mask is then stripped.
Next, as shown in FIG. 1I, a layer of spacer oxide is formed on wafer 100, and anisotropically etched away to form a number of side wall spacers 246. Once side wall spacers 246 have been formed, a NMOS source/drain mask 250 is formed and patterned on wafer 100 to protect the PMOS regions. The exposed regions of oxide layer 212 are implanted with a dopant, such as phosphorous or arsenic, to form a number of n+ source and drain regions 252 in wells 130-134. The implant also forms implanted source lines in well 130. NMOS drain mask 250 is then stripped.
After this, a PMOS source/drain mask (not shown) is formed and patterned on wafer 100 to protect the NMOS regions. The exposed regions of oxide layer 212 are implanted with a dopant, such as boron, to form a number of p+ source and drain regions 254 in wells 120-122. The PMOS mask is then stripped. The process then continues with conventional steps.
One technique for adding depletion-mode transistors to the above process flow is to utilize a separate mask and implant step to set the threshold voltages of the depletion-mode transistors. Although this is a workable solution, there is a need for a method for forming depletion-mode transistors that does not require a separate mask and implant step.
The present invention provides a method for forming a semiconductor circuit with a depletion-mode transistor that eliminates the need for a separate mask and implant step to set the threshold voltage of the depletion-mode transistor. As a result, the method of the present invention reduces the cost and complexity associated with the fabrication of a semiconductor circuit that includes a depletion-mode transistor.
In the method of the present invention, the semiconductor circuit has a first channel region, a second channel region, and a third channel region. The method includes the step of implanting the first channel region and the second channel region to add a channel dopant concentration to the first channel region and a channel dopant concentration to the second channel region. The first and second channel dopant concentrations are substantially equal.
The method also includes the step of forming a layer of first oxide on the first channel region and a layer of second oxide on the second channel region, and the step of forming a layer of first polysilicon on the layer of first oxide and a layer of second polysilicon on the layer of second oxide. The method further includes the step of etching the layer of first polysilicon to form a first gate on the first region and the layer of second polysilicon to form a second gate on the second region. The first gate has a length that is approximately 0.3 to 0.8 as long as the length of the second gate.
The present invention also includes a semiconductor circuit formed by the present method. The semiconductor circuit includes first and second transistors. The first transistor has a first channel and a layer of first gate oxide formed over the first channel. The first channel has a first channel length and a first dopant concentration, while the layer of first gate oxide has a thickness. The first transistor conducts more than a leakage current when the gate, the source, and the bulk are connected to the same potential.
The second transistor has a second channel and a layer of second gate oxide that is formed over the second channel. The second channel has a second channel length and a second dopant concentration, while the layer of second gate oxide has a thickness. The second transistor is substantially non-conductive when the gate, the source, and the bulk of the second transistor are connected to the same potential. The first channel has a first channel length approximately 0.3 to 0.8 as long as the second channel length.
A better understanding of the features and advantages of the present invention will be obtained by reference to the following detailed description and accompanying drawings which set forth an illustrative embodiment in which the principles of the invention are utilized.